Frequency divider to generate a frequency that is a multiple of a reference frequency. The latch based frequency divider are cascaded the two static differential sense amplifier pulsed latch (SSA SPL) with body biasing techniques. The operation of this type divider is to reduce power, delay and transistor size. The Adiabatic techniques dramatically reduce power consumption. This paper presents (ECRL) Efficient Charge Recovery Logic latch based frequency divider, which provides a contentment achievement. The architecture is combined two latches with feedback. Thus, frequency division is done. The circuit designed and simulation can be done in TANNER EDA.
Low power, adiabatic, ECRL, frequency divider, SSASPLlatch, body biasing technique
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